1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a nonvolatile memory device and a method for operating the same.
2. Description of the Related Art
Nonvolatile memory devices are widely used as they are electrically programmed and erased and require no refresh function for rewriting data at a constant interval.
The program and erase operations of nonvolatile memory cells are performed by changing threshold voltages of cells, where the threshold voltage changes occur due to electrons that are moved by a strong electric field applied to a thin oxide layer. In the program operation of the nonvolatile memory cell, a verify operation is performed to verify whether a program target cell is programmed with a voltage equal to or higher than a verify voltage. In the case of a single level cell (SLC) program method, only cells with two different states exist and thus a single verify voltage is used. On the other hand, in the case of a multi level cell (MLC) program method, cells with several states exist in one page and thus a plurality of verify voltages are used. According to an example, in a case in which an MSB program operation is performed in a 2-bit multi level cell program method, a verify operation may be performed based on three verify voltages.
According to an incremental step pulse program (ISPP) method, a verify operation may be performed three times after each application of a pulse. At this time, a blind verify method which does not perform each verify operation at the same time but only some of the verify operations may be used in consideration for a program speed of a cell. However, as numbers of program/erase operations of the nonvolatile memory device increases, the program speed tends to increase. Thus, a program method taking into consideration such an increase in the program speed is useful.
FIG. 1 is a view illustrating a conventional multi level cell program method of a nonvolatile memory device.
In an LSB program operation, two different cell distributions are exhibited by a program operation. More specifically, a cell distribution in which a cell is programmed with a voltage equal to or higher than a verify voltage LPV1 is referred to as a second state, and a cell distribution in which a cell is programmed with a voltage lower than the verify voltage LPV1 is referred to as a first state.
After performing the LSB program operation, an MSB program operation is performed. Due to the MSB program operation, four cell distributions (three to sixth states) having different threshold voltages are exhibited. At this time, verify voltages are different for each distribution. If arranged in ascending order, the verify voltages include a first verify voltage MPV1, a second verify voltage MPV2, and a third verify voltage MPV3. More specifically, a state that is programmed with a voltage equal to or higher than the third verify voltage MPV3 is referred to as a sixth state. A state that is programmed with a voltage lower than the third verify voltage MPV3 and equal to or higher than the second verify voltage MPV2 is referred to as a fifth state. A state that is programmed with a voltage lower than the second verify voltage and equal to or higher than the first verify voltage MPV1 is referred to as a fourth state. A state that is programmed with a voltage lower than the first verify voltage MPV1 is referred to a third state. Here, cells to be programmed to the fourth state are defined as a first verify target cell, and cells to be programmed to the fifth state are defined as a second verify target cell. Cells to be programmed to the sixth state are defined as a third verify target cell.
In the MSB program operation, the verify operation is to be performed based on more verify voltages than in the LSB program operation.
FIG. 2 is a view illustrating the concept of a conventional ISPP program method of a nonvolatile memory device.
According to the ISPP program method, a program pulse is repeatedly applied, and a verify operation is performed at every repetition. The program pulse increased by a step voltage Vstep at each repetition is applied.
As illustrated in FIG. 2, a program start voltage Vstart is initially applied, and the program voltage increased by the step voltage Vstep is subsequently applied. The verify operation is performed whenever the program pulse is applied. Therefore, the entire time spent in applying the program pulse once is equal to the sum of a program pulse application time tPULSE and a verify time tVFY.
Meanwhile, a cell distribution (that is, a threshold distribution of cells) after initially applying the program start voltage Vstart to erased cells is defined as an inherent distribution ΔVthi. The inherent distribution spanning approximately 4 V (volt) is illustrated in FIG. 2. When the program operation is performed using the program start voltage Vstart, the step voltage Vstep, and the first verify voltage PV1, the distribution of cells each having a threshold voltage higher than the first verify voltage PV1 but still lower than the maximum voltage value for the inherent distribution ΔVthi is formed. At this time, the distribution of the programmed cells in voltage may be same as the magnitude of the step voltage Vstep (that is, the step voltage increase).
According to an example, the pulse application number Npgm of pulses used for completing the program operation is determined by the ratio of the inherent distribution ΔVthi to the step voltage Vstep. For instance, when the inherent distribution ΔVthi is 4 V and the step voltage Vstep is 1 V, the pulse are to be applied four times.
Time tPROG for completing the entire program operation is equal to the product of the pulse application number Npgm and the time (tPULSE+tVFY) for applying the program pulse once.
According to the characteristics of the ISPP program, the pulse application number Npgm is reduced as the step voltage Vstep increases. Consequently, the time tPROG spent for completing the entire program operation is reduced. However, since the distribution of the programmed cells in voltage is equal to the step voltage Vstep, the overall distribution may be widened.
FIG. 3 is a view illustrating a shift of a threshold voltage according to the application of a program pulse in a conventional ISPP program method.
According to an example, the program start voltage Vstart is 16 V, the step voltage Vstep is 1 V, and the inherent distribution ΔVthi is 4 V. A target voltage to be programmed is 1-2 V, and the verify voltage is 1 V.
In the initial application of the program pulse, a program voltage Vpgm is 16 V. After the initial application of the program pulse, the threshold voltages of the cells are determined according to the inherent distribution ΔVthi. Regarding the cells programmed with 1 V or higher after the initial application of the program pulse, data stored in the page buffer is changed and thus the next program pulse is not applied.
Upon the second application of the program pulse, the threshold voltages of the cells lower than 1 V are further increased due to the application of the program pulse. Specifically, the threshold voltages of the cells lower than 1 V may be increased by 1 V. It can be seen that the distribution of the cells after the initial application of the program pulse is increased by 1 V as a whole. However, as described above, since no program pulse is applied to the cells programmed with 1 V or higher upon the initial application of the program pulse, there is no further variation created in the threshold voltages of the corresponding cells.
In addition, at each of the third and fourth applications of the program pulse, the threshold voltage is increased by 1 V. Here, as described above, the distribution of the threshold voltage in the program completion state is identical to the magnitude of the step voltage.
FIG. 4 is a view illustrating a distribution variation according to different values of a program start voltage in a conventional ISPP program method.
Depending on whether the program start voltage Vstart is 16 V or 17 V (the inherent distribution ΔVthi is 4 V and the step voltage is 1 V), the distribution of the threshold voltage is different when the program operation is completed. More specifically, as the program start voltage Vstart becomes higher, the maximum threshold voltage further increases. According to an example, when the program start voltage Vstart is 16 V, the maximum threshold voltage is 2 V. When the program start voltage Vstart is 17 V, the maximum threshold voltage is 3 V. In this case, although the maximum threshold voltages in the program completion state are different, the distributions of the threshold voltage in both cases are equal to 1 V. As described above, this is because the distribution of the threshold voltage is determined by the step voltage Vstep.
As such, the program completion states differ according to variations in the program start voltage Vstart. In both cases, however, the program pulse application count number and the time for performing the program operation are same. In light of these characteristics, when the program operation is to be performed in the MLC program operation having several threshold voltage distribution states, one program start voltage may be commonly used. More specifically, over-program can be prevented when the program start voltage is set based on a cell having the lowest target threshold voltage.
According to an example, in a case in which the target threshold voltage is 1-2 V, if the program start voltage is set to 17 V, cells have a threshold voltage of 2-3 V due to the initial application of the program pulse, as illustrated in FIG. 4. Such cells are considered to have been over-programmed. Therefore, the program start voltage is set to 16 V when the program operation is performed.
FIG. 5 is a view illustrating a variation in a program speed of a nonvolatile memory device according to the number of program/erase operations.
In using the nonvolatile memory device, the program operation and the erase operation may be repeated several times. The program operation is performed on a page basis, and the erase operation is performed on a block basis. As the program/erase cycle number increases, the program speed of the nonvolatile memory device tends to get faster. More specifically, as the number program/erase operations increases, more charges tend to get trapped into a floating gate of the nonvolatile memory device. Thus, the program speed increases as compared to the conventional cells. At this time, the program speed may be defined as a variation of a threshold voltage with respect to one-time (that is, initial) application of a program pulse.
Therefore, in addition to the inherent distribution ΔVthi, which is the factor determining the program pulse application count number Npgm of the ISPP, the variation according to the increase in the number of the program/erase operations is to be additionally considered. The variation increases as the program/erase cycle number increases.
If the program start voltage is set in light of these characteristics, the program start voltage is to be set lower than in a case where a number of performed program/erase operations is minimal. More specifically, the low program start voltage is applied at the initial operation of the nonvolatile memory device in light of a change in the program speed according to the increase in the program/erase cycle number. Such a configuration has an effect that actually applies a dummy program pulse until it reaches a specific program/erase cycle number from the initial operation. Thus, the time for performing the program operation increases.
FIG. 6 is a view illustrating a conventional blind verify method of the nonvolatile memory device.
The blind verify method may be applied to the MLC program method. The specific example of a verify method illustrated in FIG. 6 is a verify method for use in a 2-bit multi level cell program operation. The verify operation is performed based on three verify voltages PV1, PV2 and PV3. Since the verify operation is performed based on the three verify voltages, the three-time verify operations is to be performed after the initial application of the program pulse.
However, as described above, since the program start voltage is set based on the lowest threshold voltage, no cells are programmed with the second verify voltage PV2 and the third verify voltage PV3 or higher, upon the initial application of the program pulse. More specifically, after the program pulse is somewhat applied, the cells are programmed with the second verify voltage PV2 and the third verify voltage PV3 or higher. Therefore, in order to reduce the time for performing the verify operation, only the verify operation based on the first verify voltage PV1 is performed after the program pulse during first several periods. Since some verify operations are skipped, the above-described verify method is called a blind verify method. In the blind verify method, the following features may occur when applying the program pulse applying method considering the variation in the program speed according to the program/erase verifying cycle number.
FIG. 7 is a view illustrating the concept of a conventional program/verify method with respect to an MSB program of a nonvolatile memory device.
According to a first program/verify method, only a verify operation based on a first verify voltage MPV1 is performed after an initial application of a program pulse, as described above in the blind verify method. In principle, verify operations based on a second verify voltage MPV2 and a third verify voltage MPV3 is to be performed. However, only the verify operation based on the first verify voltage is performed according to the above-described blind verify method.
After the program pulse application and the verify operation based on the first verify voltage are performed three times, the verify operations based on the first verify voltage and the second verify voltage are performed. In addition, after the verify operations based on the first verify voltage and the second verify voltage are performed three times, the verify operation based on the third verify voltage is performed. Meanwhile, the number of the verify operation based on the first verify voltage and the number of the verify operations based on the first and second verify voltages may be previously set.
A second program/verify method will be described below. The second program/verify method applies a lowered program start pulse in order to compensate for the tendency where the program speed increases as the program/erase cycle number increases. More specifically, as illustrated in FIG. 7, the lower program start pulse is applied as compared to the first program/verify method. However, such a compensation may not fully counter all features that occur according to the program/erase cycle number.
More specifically, since the program speed is fast when the program/erase cycle number is large, the variation in the threshold voltage is large even when a low program pulse is applied. Therefore, the verify operation is to be performed even when a low program voltage is applied. In addition, after the point of time (A) when the threshold voltage slightly rises, the verify operations based on the first and second verify voltages is to be performed.
However, since the program speed is slow when the program/erase cycle number is small, the variation in the threshold voltage from the application of a low program pulse is small. Therefore, when a low program voltage is applied, the need to perform the verify operation is reduced/obviated. In addition, since the increase in the threshold voltage is small, the need to perform the verify operation based on the second verify voltage after the verify operation based on the first verify voltage is reduced/obviated after the program pulse is increased to some degree (that is, after “A”).
FIG. 8 is a view illustrating a conventional program/verify method of a nonvolatile memory device.
Referring to FIG. 8, when the above-described blind verify method is methodically applied to the nonvolatile memory device, the verify operation based on the second verify voltage, as well as the verify operation based on the first verify voltage, may be unnecessarily performed in the initial operation in which the program/erase cycle number is small.
In order to prevent such an operation, a blind verify method may be applied, for example, only when a cell programmed with a voltage equal to or higher than the first verify voltage is detected.
More specifically, as shown, the first verify operation based on the first verify operation, and the ISPP program operation are alternately performed until a cell programmed with a voltage equal to or higher than the first verify voltage is detected. When the cell programmed with a voltage equal to or higher than the first verify voltage is detected, the program pulse application count number applied until the detection is stored, and the above-described blind verify method is performed by adjusting a program start voltage, based on the stored program pulse application count number, when another page region is programmed.
According to an example, a nonvolatile memory device may count the program pulse application count number applied until the cell programmed with a voltage equal to or higher than the first verify voltage is detected, while programming a first page region. It can be seen from FIG. 8 that the program pulse application count number applied to the first page region is 4. Therefore, a voltage corresponding to the sum of the program start voltage for the first page region and four times the step voltage is set as the program start voltage for the second page region. Since the program start voltage for the second page region is variably set based on the program result of the first page region, time for applying the dummy program pulse may be reduced. More specifically, as in the case of FIG. 8, time for applying the dummy program pulse four times and performing the verify operation during the operation of programming the second page region may be reduced.
Meanwhile, in a nonvolatile memory device, a latch included in a controller is used to store the program pulse application count number applied until the cell programmed with a voltage equal to or higher than the first verify voltage is detected.
A nonvolatile memory device may often include tens or hundreds of page regions. Thus, in order to store the program pulse application count numbers of all page regions included in the nonvolatile memory device, as many latches as the number of page regions are to be provided inside the controller. However, such a configuration is not practical.
Therefore, in a nonvolatile memory device, the program start voltage adjustable through the program operation of the set page regions is applied to the plurality of page regions adjacent to the set page regions where a small number of latches corresponding to a set portion of page regions are included in the controller.
However, if a difference in for example, process, the number of program cycles, etc. between the two page regions occurs, data may not be normally detected when the same value is applied to the two page regions, even if two page regions are adjacent to each other. Thus, a margin considering a difference between the two page regions is to be provided, even for two page regions adjacent to each other.
According to an example, even though a cell programmed with a voltage equal to or higher than the first verify voltage by the operation of applying the program pulse four times is detected upon programming a certain page region, cells programmed with a voltage equal to or higher than the first verify voltage by the operation of applying the program pulse two times or three times under the same condition may exist in an adjacent page region.
Thus, the method for operation as described above sets a margin in light of all factors including a semiconductor chip or operation plan. Here, a difference may occur in the performance of the program/verify method of the nonvolatile memory device according to the set margin.